The retention time of Dynamic Random Access Memory (DRAM) bit cells is determined by many factors such as the size of the bit cell capacitor, the operating voltage, the capacitance of the bitline, and the semiconductor process. In a typical DRAM, the bit cells do not have identical retention times. Rather, there is some cell-to-cell variation in retention times that typically conforms to a statistical distribution function.
The cells having retention times in the lower tail of this distribution curve are sometimes referred to as “weak” cells. The weak cells are randomly distributed across the DRAM, and their locations vary from DRAM to DRAM. These weak cells affect the yield (ratio of good die to total die on a wafer), determine the refresh interval of the DRAM, and may also cause single bit errors during operation.